搜索资源列表
serialdivider-model
- this is serial divider model vhdl file and testbench not included
pci_code
- PCI接口程序，采用VHDL语言，包括主程序和testbench文件-PCI INTERFACE IN VHDL
spi_master
- 用VHDL编写的一个SPI主机程序，SPI模块采用最常用的模式0方式（即CPOL=0,CPHA=0）通信。文件内含测试文档，已在Modelsim6.5上测试通过，可在FPGA上直接调用。-A SPI Master code edited by VHDL language,the SPI modul use 0 MODE(i.e CPOL=0,CPHA=0)to communicate with the SPI Slave.and there is a testbench in the file
vhld_tb_latest.tar
- 一个VHDL的测试平台，可以用来验证MircroProcessor，有完备的文档和代码。-A testbench based on VHDL language, you can apply it to verify a simple mircroprocessor, include complete ducoment and sources
pplllrarl
- 用VHDL写的数字锁相环程序源码 pll.vhd为源文文件 pllTB.vhd为testbench 可直接使用。 -Written using VHDL digital PLL pll.vhd program source code for the source text file pllTB.vhd testbench can be used directly.
six-digit-counter-with-tb
- VHDL source code of six digit counter with testbench,with comments included
2-to-4-Decoder-with--Configuration
- 2-to-4 Decoder with Testbench and Configuration This set of design units illustrates several features of the VHDL language including: Using generics to pass time delay values to design entities. Design hierarchy using instantiated components.
Full-Adder
- 用VHDL实现的全加器，采用dataflow style编写，是学习VHDL入门级的好范例. 包括主程序和测试程序-Full adder by using VHDL, dataflow style writing. It is a good example of VHDL especially for the entry-level leaner（Testbench included）
counter2b
- 基于vhdl完成4位计数器功能的实现，并基于此程序完成16位加法器程序的编写，内附testbench,测试成功。-Based on the vhdl completed four counter function to achieve, and the completion of a 16-bit adder program written based on this program, enclosing testbench, the test is successful.
mux-top-module
- Vhdl implementation of Mux module using and gate or gate and with testbench
lab5_
- 这是在vhdl开发环境下模拟D-FLI FLOP,T-FLIP FLOP 和 JK-flip flop。其中包含testbench 源码。-This is the vhdl development environment simulation D-FLI FLOP, T-FLIP FLOP and JK-flip flop. Which contains the testbench source.
FPGABitcoinMiner
- 比特币的FPGA挖币机中SHA256的核心代码及测试用例，适合于自己开发比特币挖币机-vhdl based SHA256 computation code and testbench for bitcode miner. For developers that build their own mining machines
FIR-filter
- VHDL设计的FIR滤波器，由3个文件组成：FIR.VHD、PACK.VHD和signed.vhd。testfir.vhd为测试平台。-VHDL designed FIR filters, composed by the three documents: FIR.VHD, PACK.VHD and signed.vhd. The testfir.vhd is a testbench.
SDRAM_Modelsim
- 基于VHDL的SDRAM控制器源代码以及modesim验证工程的testbench-SDRAM controller based on VHDL source code and modesim verification testbench works
ethenete
- 基于verilog的三速以太网源程序，文件中包含源程序和测试程序。-tri_model ethernet source code based on vhdl languange, include source code and testbench in the file.
ALU
- 简易的VHDL程序，主要实现ALU的逻辑功能，进行选择和数据的移动。很适合初学者对VHDL的理解。内含有testbench可以进行Qutarus的仿真-Simple VHDL program, the main achievement of the ALU logic functions, to select and move data. VHDL is suitable for beginners to understand. Containing a simulation testbench
dac7564
- 基于VHDL的dac7564驱动程序和该程序的testbench测试程序-I DON T KOWN
yimaqi_beh
- 8位计数器作业中的behavioral描写，没有带testbench，已经通过-1. Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption types, i.e., behavioral, dataflow and structural descr iptions. Synthesize and simulate these models respectively in the en
hamming
- 32位海明码编码解码的vhdl代码，有testbench验证。-32 Hamming code encoding and decoding of vhdl code, testbench verification.
mcu8051
- 一个实现MCU51处理器的完整VHDL源代码，包含testbench-An implementation MCU51 processor complete VHDL source code, including testbench